The present invention relates to a display device and a method of manufacturing the same, and particularly to a liquid crystal display device and a method of manufacturing the same.
With characteristics of being thin and low power consumption, liquid crystal display devices are widely used in notebook computers, display devices for car navigation, personal digital assistants (PDAs), portable telephones and the like. The liquid crystal display device is roughly classified into a transmissive type that controls light from a backlight for display, a reflective type that reflects extraneous light such as sunlight or the like for display, or a recent display device referred to as a transflective type that combines characteristics of both the transmissive type and the reflective type.
Applications of these display devices require that the display devices consume low power, and therefore a high aperture ratio is required to maximize efficiency of use of the backlight. In the transflective type, a transmission part and a reflection part are formed in the same pixel, and thus multiple functions are incorporated within the pixel; it is therefore necessary to use space as effectively as possible.
In displaying an image on a liquid crystal display device, a scanning pulse is applied from a scanning line to a switching element, for example a TFT (Thin Film Transistor) provided for each pixel, and the switching element is turned on/off, whereby display pixels are selected. A signal corresponding to a video signal is applied to a data line, and then applied via a source and a drain of the TFT to electrodes that have a liquid crystal sandwiched therebetween, whereby light entering the liquid crystal is modulated to display the image.
Within a period until a next writing operation after a voltage corresponding to the video signal is written to each pixel, charge resulting from the voltage applied to the electrodes of the liquid crystal leaks through the liquid crystal and the switching element and is thus changed. In order to insure display picture quality, the applied voltage needs to be retained. Accordingly, an auxiliary capacitance (CS) sufficient as compared with the amount of leakage is generally formed in the liquid crystal display device.
FIG. 1 is an example of an equivalent circuit diagram of a conventional liquid crystal display device. FIG. 2 is a plan view of a configuration of the liquid crystal display device shown in FIG. 1.
FIG. 1 shows an equivalent circuit of 2×3 pixels. One pixel in the equivalent circuit includes a liquid crystal element and electrodes having the liquid crystal element sandwiched therebetween, a transistor Tr as a switching element, and an auxiliary capacitance CS. Ccl1 to Ccl6 denotes a capacitance of a liquid crystal capacitor formed by a liquid crystal element and a display electrode and a common electrode having the liquid crystal element sandwiched therebetween. CS1 to CS6 denotes a capacitance value of the auxiliary capacitance of each pixel.
A plurality of scanning lines WLn−1, WLn, and WLn+1 are arranged in parallel with each other, and each connected to gate electrodes of transistors Tr1 and Tr4, transistors Tr2 and Tr5, or transistors Tr3 and Tr6 formed by TFTs, for example. The scanning lines WLn−1, WLn, and WLn+1 effect ON/OFF control of each of the transistors and thereby select pixels.
Data signal lines BLn−1, BLn, and BLn+1 arranged in parallel with each other apply a voltage corresponding to a video signal to each pixel. The data signal lines BLn−1, BLn, and BLn+1 are connected to for example a source region of the transistors Tr1, Tr2, and Tr3 or the transistors Tr4, Tr5, and Tr6. The data signal lines BLn−1, BLn, and BLn+1 apply voltage to electrodes on both sides of liquid crystal elements in pixels selected by the scanning line WLn−1, WLn, or WLn+1 while charging auxiliary capacitances CS in the pixels, whereby light entering the liquid crystal elements is modulated to display an image.
FIG. 2 is a view of the configuration of scanning lines, data signal lines, and one pixel formed on a transparent substrate. As shown in FIG. 2, the auxiliary capacitance CS1 is formed on an auxiliary capacitance line CSLn−1 as one electrode of the auxiliary capacitance CS1. One impurity region, for example the source region of the transistor Tr1 is connected to the data signal line BLn−1 via a conductive material deposited in a contact hole H1. Another impurity region, for example a drain region of the transistor Tr1 is connected to another electrode formed by a semiconductor, for example, of the auxiliary capacitance CS1 and an ITO electrode of an upper layer not shown in the figure via conductive material deposited in contact holes H2 and H3.
An N-channel type thin film transistor TFT is generally used as the transistors Tr1, . . . , Tr6. Specifically, N-type source and drain impurity regions are formed by injecting phosphorus (P) or the like into semiconductor thin film on both sides of a gate electrode. When a positive voltage equal to or higher than a threshold value is applied to the gate electrode (scanning line), an N-channel formed by an N-type inversion layer is formed between the source and the drain, whereby the source and the drain are electrically connected to each other. That is, the transistor is in an ON state. When a voltage lower than the threshold value is applied to the gate electrode (scanning line), on the other hand, the channel for electrically connecting the source and the drain to each other is not formed, and therefore the transistor is in an OFF state.
The auxiliary capacitance CS1 is generally formed by a MOS structure of a semiconductor layer, an insulating film, and a metal, which structure can form a highest capacitance. In FIG. 2, the auxiliary capacitance CS1 is for example formed by the auxiliary capacitance line CSLn−1 (metal), a gate insulating film forming the transistor Tr1, and the above-mentioned N-type semiconductor film having phosphorus or the like injected therein. Such a MOS capacitance will hereinafter be referred to as an N-type MOS structure.
When the electrodes of the auxiliary capacitance are to be set at a fixed potential, the auxiliary capacitance portion is generally made to be of the N-type MOS structure.
In a case of common-inversion driving in which auxiliary capacitance electrodes are oscillated in phase with a counter electrode, the semiconductor film forming the auxiliary capacitance CS does not form a sufficient capacitance in an intrinsic state. Therefore, the semiconductor layer is generally metalized, that is, made to contain a high concentration of phosphorus (made to be of an N+ type) or boron (made to be of a P+ type).
With the above conventional method, high-concentration injection of phosphorus (allowing the semiconductor layer to be of the N+ type) or boron (allowing the semiconductor layer to be of the P+ type) is required to be performed only once, and therefore manufacturing cost can be reduced.
However, the above structure requires an independent auxiliary capacitance line, thus presenting a problem of a decrease in an aperture ratio.
Accordingly, a CS-on-gate structure is proposed in which a scanning line (gate line) in a preceding stage or a succeeding stage also serves as the auxiliary capacitance line.
FIGS. 3A and 3B show another example of a conventional liquid crystal display device. FIG. 3A is an equivalent circuit diagram of the liquid crystal display device, and FIG. 3B is a plan view of a configuration of the liquid crystal display device. In FIGS. 3A and 3B, the same components as in FIG. 1 are designated by using the same reference numerals, and their repeated description will be omitted where appropriate.
FIG. 3A shows an equivalent circuit of 2×2 pixels. In FIG. 3A, auxiliary capacitances CS1, CS4, CS2, and CS5 are directly connected to scanning lines WLn−1, WLn, and WLn+1 in place of the auxiliary capacitance lines CSLn−1, CSLn, and CSLn+1 shown in FIG. 1.
FIG. 3B shows a configuration of scanning lines, data signal lines, and one pixel formed on a transparent substrate. The auxiliary capacitance CS1 is formed so as to overlap the scanning line WLn in place of the auxiliary capacitance line CSLn−1 shown in FIG. 2.
Also in this case, an N-channel type thin film transistor TFT is generally used as transistors Tr1, . . . , Tr6. Also, the auxiliary capacitance CS1 is an N-type MOS capacitance. Specifically, when a positive voltage equal to or higher than a threshold value is applied to gate electrodes (scanning lines) of the transistors Tr1, . . . , Tr6, the transistors Tr1, . . . , Tr6 are brought into an ON state. When a voltage lower than the threshold value is applied to the gate electrodes, the transistors Tr1, Tr6 are brought into an OFF state.
As shown in FIG. 3B, the auxiliary capacitance CS1 is formed by the scanning line WLn (metal), a gate insulating film forming the transistor Tr1, and an N-type semiconductor film having phosphorus or the like injected therein.
Such a CS-on-gate structure eliminates the need for forming the independent auxiliary capacitance line, and therefore has an advantage of increasing the aperture ratio.
In order to maintain the NMOS transistor Tr1 in an off state, the potential of the scanning lines WLn−1, WLn, . . . may generally be set to about 0 V to −6 V. In addition, the transistor Tr1 in the liquid crystal display device is maintained in the OFF state during most of a period of display of one screen. That is, the potential of the scanning lines is maintained at 0 V or lower during most of the display period.
However, in the case of the CS-on-gate structure as shown in FIGS. 3A and 3B, in which structure the auxiliary capacitance CS1 is formed with the scanning line (gate line) WLn in the succeeding stage, for example, and the potential as described above is applied, the N-type MOS structure formed by the scanning line, the gate insulating film, and the N-type semiconductor film cannot provide a sufficient capacitance.
FIG. 4 is a graph showing capacitance-voltage characteristics of the N-type MOS structure.
When −2 V, for example, is applied to the scanning lines WLn−1 and WLn shown in FIG. 3B and thereby Tr1 is maintained in an OFF state, since CS1 is charged while Tr1 is in an ON state, the semiconductor electrode of CS1 is at a higher potential than the scanning lines WLn−1 and WLn, and the gate voltage applied to CS1 is a negative voltage. This causes majority carrier electrons to be repelled from a surface of the semiconductor film and a depletion layer (and/or an inversion layer) to be formed on the surface of the semiconductor film, which corresponds to an increase in thickness of the insulating layer of CS1. Thus, a resulting capacitance is small.
This tendency is shown in FIG. 4. When the scanning potential is used in a range of about 1.5 V and lower, only a small capacitance is provided by the N-type MOS capacitance at all times.
In order to increase the capacitance of the auxiliary capacitance CS1, phosphorus (for making an N+ type) or boron (for making a P+ type) needs to be injected at a high concentration into the semiconductor film electrode of the auxiliary capacitance CS1. This causes problems of an increase in the number of processes, a decrease in yield resulting from occurrence of defects, and the like.
FIGS. 5A to 7B illustrate an example of a process of manufacturing the conventional liquid crystal display device.
In FIG. 5A, gate electrodes (scanning lines) 102a and 102b serving as scanning lines are formed on a glass substrate 101. A metal such as Ta, Cr, Mo, Ti, Al or the like is used for the material of the gate electrodes, and the pattern is formed by wet etching or dry etching following a photoresist process.
In FIG. 5B, an gate insulating film 103 and a semiconductor layer 104a are formed over the gate electrodes 102a and 102b. Examples of the gate insulating film 103 include silicon nitride film and silicon oxide film, as well as anodized film obtained by anodizing a gate electrode and the like. As the semiconductor film, amorphous silicon film, polysilicon film obtained by crystallizing amorphous silicon film, polysilicon film formed directly, or the like is used.
In FIG. 5C, a protective insulating film 105 is formed on the semiconductor film 104a. As the protective insulating film 105, silicon nitride film, silicon oxide film or the like is used.
In FIG. 5D, resists 107a and 107b are formed in a self-aligning manner with the gate electrodes 102a and 102b serving as a light shield mask. The protective insulating film 105 is thereafter removed by wet etching or dry etching. Then, using remaining protective insulating films 105a and 105b as a mask, the semiconductor film is doped with phosphorus (P) or the like at a low concentration. A doped portion of the semiconductor film is denoted as 104b. The semiconductor film 104b is an n− type semiconductor.
In FIG. 6A, a resist 108 having such a shape as to cover a portion forming an LDD region in the pixel transistor is formed. In order to remove the protective insulating film 105b remaining in a portion where the auxiliary capacitance is formed, wet etching or dry etching is thereafter performed.
Then, phosphorus or the like is injected at a high concentration to thereby metalize the semiconductor layer 104b. A metalized portion of the semiconductor film 104b is denoted as 104c. 
Though not shown in the figures, a photoresist process and an injection process are carried out according to a portion for injection of a second type of dope (boron or the like). Thereafter heat treatment is performed as required to activate doped elements.
The wet etching or the dry etching is usually performed by a process with etching selectivity to protect the semiconductor layer 104b from the etching. However, when there is a pin hole or the like in the semiconductor layer 104b, the gate insulating film 103 serving as a base is etched. The etched portion, being greatly deteriorated in terms of withstand voltage, forms a path of current leakage, and causes a defect such as a point defect or the like. Besides, the process for removing the protective insulating film 105b is added, which represents a cost increasing factor.
In FIG. 6B, for device isolation, the semiconductor layer 104c on the outside of the gate electrodes 102a and 102b is removed using means such as photolithography, dry etching or the like.
In FIG. 6C, an interlayer insulating film 109 is formed by silicon nitride film, silicon oxide film or the like. Thereafter contact holes 110a and 110b are formed using means such as photolithography, wet etching or the like.
In FIG. 7A, a metal such as Al, Ta, W or the like is formed as data signal lines 111a and 111b and a connecting metal 112 for connection with a pixel electrode. Thereafter the metal is removed using means such as photolithography, dry etching or the like, whereby a pattern is formed.
In FIG. 7B, a second interlayer insulating film 113 is formed by silicon nitride film, silicon oxide film or the like. In order to provide this layer with a flattening effect, a photosensitive organic film, a photosensitive SOG (spin on glass) film or the like may be used. Also in this process, a contact hole for connection with the pixel electrode 114 is formed. Thereafter the pixel electrode 114 is formed using a transparent conductive film of ITO, IXO or the like.
Then, though not shown in the figures, a corresponding color filter substrate prepared separately is superposed on the TFT substrate, an assembly process is carried out with a liquid crystal layer sandwiched between the color filter substrate and the TFT substrate, and further a polarizer and the like are attached, whereby the liquid crystal display device is completed.
Thus, with the conventional manufacturing method, a special process is required to complete the structure of the auxiliary capacitance, which constitutes a cost increasing factor, and also leakage current that causes defects is increased. There are conventionally problems of such an increase in the number of processes and a decrease in yield resulting from occurrence of defects.
While a conventional example of the bottom gate type transistor in which the scanning line (gate electrode) is formed under the semiconductor layer has been described above, there are also problems in a method of manufacturing the top gate type transistor in which the scanning line (gate electrode) is formed above the semiconductor layer.
FIGS. 8A, 8B, and 8C and FIGS. 9A and 9B illustrate a conventional example of a method of manufacturing a liquid crystal display device having the structure of the top gate type transistor.
As shown in FIG. 8A, a base layer 122 and a semiconductor layer 123a are formed on a glass substrate 121. As the base layer 122, silicon nitride film or silicon oxide film, for example, is used. As the semiconductor layer 123a, amorphous silicon film, polysilicon film obtained by crystallizing amorphous silicon film, polysilicon film formed directly, or the like is used.
As shown in FIG. 8B, in order to obtain a region for device isolation, a part of the semiconductor layer 123a is removed using means such as photolithography, dry etching or the like.
A gate insulating film 124 is then formed on the semiconductor film 123a. Examples of the gate insulating film include silicon nitride film, silicon oxide film and the like.
Then, gate electrodes 125a and 125b are formed in a region for forming a transistor TFT and a region for forming an auxiliary capacitance.
Next, the semiconductor film is doped with phosphorus or the like at a low concentration in a self-aligning manner with the gate electrodes 125a and 125b serving as an injection mask. A doped portion of the semiconductor film is an n− type semiconductor, and is denoted as 123b. 
As shown in FIG. 8C, a resist 126 having such a shape as to cover a portion forming an LDD region in the pixel transistor TFT is formed. Phosphorus or the like is injected into other regions at a high concentration to thereby metalize the semiconductor layer 123b. The metalized portion of the semiconductor film 123b is denoted as 123c. 
Though not shown in the figures, a photoresist process and an injection process are carried out according to a portion for injection of a second type of dope (boron or the like). Thereafter heat treatment is performed as required to activate doped elements.
In FIG. 9A, an interlayer insulating film 127 is formed by silicon nitride film, silicon oxide film or the like. Thereafter contact holes 128a and 128b are formed using means such as photolithography, wet etching or the like.
In FIG. 9B, a metal such as Al, Ta, W or the like is formed as data signal lines 129a and 129b and a connecting metal 130 for connection with a pixel electrode 132. Thereafter the metal is removed using means such as photolithography, dry etching or the like, whereby a pattern is formed.
Then, a second interlayer insulating film 131 is formed by silicon nitride film, silicon oxide film or the like. In order to provide this layer with a flattening effect, a photosensitive organic film, a photosensitive SOG (spin on glass) film or the like may be used. Also in this process, a contact hole for connection with the pixel electrode 132 is formed. Thereafter the pixel electrode 132 is formed using a transparent conductive film of ITO, IXO or the like.
Then, though not shown in the figures, a corresponding color filter substrate prepared separately is superposed on the TFT substrate, an assembly process is carried out with a liquid crystal layer sandwiched between the color filter substrate and the TFT substrate, and further a polarizer and the like are attached, whereby the liquid crystal display device is completed.
As shown in FIGS. 8B and 8C, the above structure has the gate electrode 125b formed in a region for forming the auxiliary capacitance. Therefore no impurity can be injected into the semiconductor film 123a under the gate electrode 125b, and the semiconductor film 123a under the gate electrode 125b cannot be metalized. In order to solve this problem within the scope of the conventional method, it is necessary to add processes of forming a mask, performing injection, and then removing the mask in an initial stage, or form an independent auxiliary capacitance line as shown in FIG. 1.